三菱IGBT应用的若干问题

IPM/IGBT 的若干应用问题

2. IGBT的栅极驱动设计
典型栅极驱动电路框图

采用驱动IC驱动
直接驱动

经过一级放大后驱动(用来驱动大电流模块)

2-1. 栅极驱动电压VG

开通电压(正电压)：+VG= 15V (±10%)关断电压(负偏压)：-VG= 5~10V

2-2. 栅极电阻RG

推荐在所给的标准值(Min.)与10倍标准值(Max.)之间选择。

2-3. 栅极驱动功率要求驱动电流的峰值：

驱动电流的平均值：

其中，ΔVGE= VGE(on)+ |VGE(off)|

QG= 总栅极电荷

f = 开关频率

驱动电路布线设计注意事项
1.The layout must minimize the parasitic inductance between the driver’s output stage and the IGBT. This corresponds to keeping the loop area assmall as possible showed in the following Figure.

2. Care must be taken to avoid coupling of noise between the power circuit and the control circuit. This can be accomplished by proper placement ofthe gate drive board and/or shielding the gate drive circuit.
3. It is recommended to use the auxiliary emitter terminal for connecting the gate drive.

4. If direct connection of the drive PCB to the IGBT control terminals is not possible, the use of twisted pair (3 turns per inch of minimum length) or strip line is recommended.
5. Gate protection clamp must also have low inductance layout and must be located as close as possible to the gate-emitter control terminals of the IGBT module.
6. Do not route printed circuit board traces near each other that are subjected to mutual potential changes due to IGBT switching. High dv/dtcan couple noise through parasitic capacitances. If crossing or parallel routing of those traces is unavoidable, use shield layers in between.
7. Parasitic capacitance between high side gate drive circuits, high and low side gate drive circuits and control circuits may cause problems with coupled noise. Power supply transformer inter-winding capacitance can be another source of coupled noise. Appropriate measures to reduce these parasitic capacitances have to be implemented.
8. If opt-couplers are used for isolation of the high side gate drive signals they should have a minimum common mode transient immunity of 10,000 V/μs.